The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 27, 2001
Filed:
Aug. 27, 1999
Applicant:
Inventor:
Pradeep Katikaneni, Austin, TX (US);
Assignee:
Cypress Semiconductor Corp., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 1/90175 ;
U.S. Cl.
CPC ...
H03K 1/90175 ;
Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a differential intermediate signal in response to a differential input signal. The second circuit may be configured to generate one or more output signals in response to said differential intermediate signal.
Katikaneni, Pradeep. (2001). Low distortion logic level translator (U.S. Patent No. 6323683). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6323683
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile