The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 27, 2001
Filed:
Nov. 02, 2000
Adam J. Whitworth, Sunnyvale, CA (US);
Dominick Richiuso, Saratoga, CA (US);
California Micro Devices Corporation, Milpitas, CA (US);
Abstract
An active termination circuit for clamping a signal on a transmission line in an electronic device in a tri-state mode is described. The active circuit includes a tri-state output buffer and a bottom clamping transistor coupled to GND and the tri-state output buffer having a bottom clamping transistor control node arranged for clamping the signal at about GND. A bottom threshold reference transistor coupled to a first reference voltage supply configured to supply a first reference voltage. The bottom threshold reference transistor provides a first bias voltage to the bottom clamping transistor control node that biases the bottom clamping transistor control node at about a first threshold voltage above GND where the first threshold voltage represents a threshold voltage of the bottom clamping transistor. A top clamping transistor coupled to VDD and the tri-state output buffer having a top clamping transistor control node arranged for clamping said signal at about VDD and a top threshold reference transistor coupled to a second reference voltage supply configured to supply a second reference voltage. The top threshold reference transistor provides a second bias voltage to the top clamping transistor control node that biases the top clamping transistor control node at about a second threshold voltage from VDD where the second threshold voltage represents a top clamping transistor threshold voltage.