Semiconductor memory device capable of accurately testing for defective memory cells at a wafer level

Abstract

Disclosed herein is a semiconductor memory device that includes a memory cell array and a plurality of pads for providing data to and from the memory cell array. A plurality of input/output line pairs corresponds to the plurality of pads. A reading means reads out the data from the memory cell array through the plurality of input/output line pairs and pads. A switch control circuit generates sequential switch control signals during a test mode. A switch control means receives the data from the reading means during the test mode. The switching means sequentially transfers the data to a representative pad responsive to the switch control signals. The present invention allows testing for defective memory cells at a wafer level using a limited number of probe needles.