The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2001

Filed:

Jun. 29, 1999
Applicant:
Inventors:

John Edward Derrick, Round Rock, TX (US);

Lee Evan Eisen, Austin, TX (US);

Kevin Franklin Reick, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/212 ;
U.S. Cl.
CPC ...
G06F 1/212 ;
Abstract

A “soft-patch” allows an instruction or group of instructions to be replaced with a pre-loaded instruction or group of instructions. When an Instruction Fetch Unit (IFU) fetches an instruction, the instruction is sent through a Compare and Mask (CAM) circuit which masks and compares, in parallel, the instruction with up to eight pre-defined masks and values. The masks and values are pre-loaded by a service processor to CAM circuits which are located in an Instruction Dispatch Unit (IDU) and the IFU in the central processor. An instruction that is deemed a match, is tagged by the IFU as a “soft-microcode” instruction. When the IDU receives the soft-microcode instruction for decoding, it detects the soft microcode marking and sends the marked instruction to a soft-microcode unit; a separate parallel pipeline in the IDU. The soft-microcode unit then sends the instruction through a CAM circuit which returns an index (or address) for RAM. The index is used to read values out of IDU RAM and generate replacement instructions. Additionally, an Internal Operation that will cause the processor core to perform an unconditional branch to a fixed real address, can be loaded into the IDU RAM allowing an instruction to be replaced by a subroutine or handler routine contained outside the processor core.


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