The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 20, 2001
Filed:
Mar. 16, 1999
Katsuyoshi Suzuki, Hadano, JP;
Toru Hiyama, Yokohama, JP;
Hitachi, Ltd., Tokyo, JP;
Abstract
Optimal layout of logic elements of semiconductor integrated circuits is achieved in conformity with the intention of the logic designer in a short period of time in an interactive mode. When logic blocks are to be laid out on a display screen, a logic block file consisting at least of logic block names, logic block sizes, and information on connection relationships with other logic blocks is used, and logic blocks essential for the designer's intention are laid out in random positions on a display screen, and then the connection relationships among the logic blocks are displayed according to the logic block file. In this procedure, whether the layout is appropriate or not is made readily recognizable by a table of relationships among the logic blocks.