Executing debug instructions

Abstract

Apparatus for processing data is provided, said apparatus comprising: a main processor,driven by a main processor clock signal clk at a main processor clock frequency; debug logic,at least a portion,of which is driven by a debug clock signal tck at a debug clock frequency, said debug clock frequency being different to said main processor clock frequency and said main processor clock signal clk being asynchronous with said debug clock signal tck; and an instruction transfer register ITR into which a data processing instruction may be transferred by said debug logic,and from which said data processing instruction may be read by said main processor,wherein when switched from a normal mode to a debug mode said main processor,continues to be driven by said main processor clock signal clk executing no-operation instructions until a data processing instruction is present within said instruction transfer register ITR and said debug logic,triggers said main processor to read and execute said data processing instruction whilst still driven by said main processor clock signal clk. This arrangement allows debug instructions to be executed at full speed whilst avoiding the need to switch clock speeds and provide a synchronisation mechanism.