The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 20, 2001
Filed:
Feb. 19, 1999
Naoya Takahashi, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
Power consumption of an LSI chip is estimated at the beginning stage of the designing without using the HDL description. An I/O part power of a new designing LSI chip is calculated by an equation with using the outside specifications required by the application of the LSI chip. An I/O part power of an original LSI chip is calculated by the outside specifications, the core circuitry part power of the original LSI chip is calculated by subtracting this calculated I/O part power of the original LSI chip from the known total power of the original LSI chip, and converting the voltage and process and frequency, the core circuitry part power of the new designing LSI chip is calculated. The kinds of functions, voltage, frequency, the number of gates, unit capacity and clock structure of the new designing LSI chip are given and referring to the data base of ratio of each function described the ratio of the number of FF and the ratio of clock power/logic power, the clock system power is calculated by the number of FF and the clock structure. The logic system power is calculated by the ratio of the clock power/the logic power. The modifiable circuitry part power is calculated by summing up the I/O part power, the core circuitry part power, the clock system power and the logic system power.