The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2001

Filed:

Aug. 07, 2000
Applicant:
Inventor:

Masato Susuki, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 ;
U.S. Cl.
CPC ...
G11C 8/00 ;
Abstract

This semiconductor device is equipped with a surplus address detection circuit with a small area and the circuit can be used commonly for various maximum word sizes. The semiconductor comprises a memory for an intermediate word size having X rows or columns, where X is between Nth power of 2 and (N-1)th power of 2, and N is a natural number, an address decoder that decodes address signals addressing rows or columns of the memory for an intermediate word size to be accessed, and a surplus address detection circuit that detects accesses to surplus addresses larger than number X. The address decoder comprises plural pre-decoders that decode address signals classified into plural groups and a post-decoder that generates a selection signal that selects a row or column to be accessed by the combination of outputs of the plural pre-decoders. The surplus address detection circuit detects accesses to surplus addresses larger than number X by the outputs of the plural pre-decoders, and the number of the input signal lines of the surplus address detection circuit is smaller than that of the outputs of the plural pre-decoders, and only a part of the outputs of the plural pre-decoders is supplied to the surplus address detection circuit.


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