The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2001

Filed:

Sep. 19, 1994
Applicant:
Inventor:

Yukio Yano, Kanagawa, JP;

Assignee:

Fuji Electric Co., Ltd., Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 5/153 ;
U.S. Cl.
CPC ...
H03K 5/153 ;
Abstract

An integrated circuit including a comparator circuit and a vertical voltage control switch element formed on a single substrate. The comparator circuit including a differential amplifier circuit having a current mirror circuit M, a differential amplifier circuit D,with two current paths L,and L,, and an inverter INV. The output section of the current mirror circuit M is used as a constant current source for the differential amplifier circuit. The current mirror circuit M includes a load MOS transistor,, a MOS transistor,constituting an input section, and a MOS transistor,constituting an output section. The current path L,of the differential amplifier circuit D,includes a load MOS transistor,, an amplifying depletion type MOS transistor,, and an input terminal in,. Similarly, the current path L,includes a load MOS transistor,, an amplifying depletion type MOS transistor,, and an input terminal in,. The inverter INV is constructed with a load MOS transistor,and a switching transistor


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