The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 20, 2001

Filed:

Feb. 16, 2000
Applicant:
Inventor:

Satoru Miyoshi, Kanagawa, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/900 ;
U.S. Cl.
CPC ...
H01L 2/900 ;
Abstract

There are provided a semiconductor device which can prevent short-circuit of the contact plugs and prevent exposure of wirings to ensure sufficient reliability even if level difference is caused in device isolation regions, and a method of manufacturing the same. Device isolation regions,are formed on a semiconductor substrate,to partition the semiconductor substrate,into a plurality of device regions,. Then, word lines,are formed on the semiconductor substrate,, and then peripheral regions of the word lines,are covered with a protection film. Then, impurity diffusion regions formed in the device regions,, and then a plug insulating film is formed on an overall upper surface of the substrate,. Then, opening portions,for connecting end portions of the device regions,are formed in the plug insulating film. Then, a conductive film is buried in the opening portions,, and then the conductive film and the plug insulating film are polished by the CMP method until any one of the protection film on the device isolation regions,and the protection film on the device regions,is exposed.


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