The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 20, 2001
Filed:
Oct. 27, 1999
Hyundai Electronics Industries Co., Ltd., Kyoungki-do, KR;
Abstract
The present invention is directed to provide a manufacturing method of a liquid crystal display having high transmittance and high aperture ratio, wherein the method is capable of decreasing process time and cost by reducing numbers of photolithography process steps. The manufacturing method of the liquid crystal display according to comprises the steps of: providing a transparent insulating substrate having a displaying area and a non-displaying area; forming a light shielding pattern and a common signal line, with an opaque metal layer on the non-displaying area of the transparent insulating substrate; forming a counter electrode with a transparent metal layer on the displaying area of the transparent insulating substrate; depositing an insulating layer over the transparent insulating substrate so as to cover the light shielding pattern and the common signal line, and the counter electrode; forming source and drain electrodes to be overlapped with the light shielding pattern respectively on the insulating layer portions of both sides of the light shielding pattern and a data bus line connected to the source electrode; forming a pixel electrode with a transparent metal layer on the insulating layer portion of the displaying area; forming a channel layer on the light shielding pattern and on the source and drain electrode portion overlapped with the light shielding pattern; and forming a gate bus line having a gate insulating layer on the channel layer.