The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 13, 2001
Filed:
Apr. 19, 1996
Takumi Hasegawa, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A delay verification device includes a circuit information storing unit for storing circuit information of a logic circuit, a before layout designing delay information storing unit for storing before layout designing delay information on a delay time between circuit elements predicted before layout designing, an after layout designing delay information storing unit for storing after layout designing delay information on a delay time between circuit elements computed after layout designing of the logic circuit, a difference extracting unit for comparing the before layout designing delay information and the after layout designing delay information to extract and register difference information on a portion of the logic circuit, whose delay time of the after layout designing delay information is longer than that of the before layout designing delay information, a tracing unit for searching paths of the logic circuit to extract a path including a portion of the logic circuit corresponding to the difference information, an extracted circuit information storing unit for storing an extracted circuit information, and a delay analyzing unit for analyzing delays of the logic circuit based on the extracted circuit information and the after layout designing delay information.