The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2001

Filed:

Jul. 28, 1998
Applicant:
Inventor:

Yasuo Kobayashi, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 2/900 ; G11C 7/00 ; G06F 1/100 ;
U.S. Cl.
CPC ...
G11C 2/900 ; G11C 7/00 ; G06F 1/100 ;
Abstract

A memory test circuit in which time required for a memory test is reduced is disclosed. A memory test circuit according to the present invention is provided with stripe data generating means for generating stripe data composed of plural bits based upon a block address signal, means for writing the above stripe data to a predetermined address of a memory, means for reading information written to the above predetermined address of the memory and compare means for judging whether the above read information is the same as the stripe data or not. The above stripe data generating means generates stripe data in a cycle 2 in response to a first state of the above block address signal and generates stripe data in a cycle 4 in response to a second state of the block address signal.


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Kobayashi, Yasuo. (2001). Memory test circuit and a semiconductor integrated circuit into which the memory test circuit is incorporated (U.S. Patent No. 6317851). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6317851

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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