The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2001

Filed:

May. 08, 1998
Applicant:
Inventors:

Akihito Nagae, Tokyo, JP;

Koichi Senuma, Tokyo, JP;

Takeyuki Iguchi, Tokyo, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/26 ; G06F 1/28 ; G06F 1/30 ;
U.S. Cl.
CPC ...
G06F 1/26 ; G06F 1/28 ; G06F 1/30 ;
Abstract

The CPU speed is apparently decreased, and current consumption is reduced by asserting a stop clock (STPCLK#) signal at a predetermined interval. When a system event (INTR, NMI, SMI, SRESET, and INIT) occurs, assertion of the STPCLK# signal is inhibited for a predetermined time to allow a high-speed operation. In an ISA refresh cycle, by asserting the STPCLK# signal instead of a conventional HOLD/HLDA cycle, the refresh cycle is executed in a stop grant state.


Find Patent Forward Citations

Nagae, Akihito. (2001). Computer system using stop clock function of cpu to enter low power state (U.S. Patent No. 6317841). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6317841

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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