Digital signal processor containing scalar processor and a plurality of vector processors operating from a single instruction

Abstract

A digital data processor integrated circuit (,) includes a plurality of functionally identical first processor elements (,A) and a second processor element (,). The first processor elements are bidirectionally coupled to a first cache (,) via a crossbar switch matrix (,). The second processor element is coupled to a second cache (,). Each of the first cache and the second cache contain a two-way, set-associative cache memory that uses a least-recently-used (LRU) replacement algorithm and that operates with a use-as-fill mode to minimize a number of wait states said processor elements need experience before continuing execution after a cache-miss. An operation of each of the first processor elements and an operation of the second processor element are locked together during an execution of a single instruction read from the second cache. The instruction specifies, in a first portion that is coupled in common to each of the plurality of first processor elements, the operation of each of the plurality of first processor elements in parallel. A second portion of the instruction specifies the operation of the second processor element. Also included is a motion estimator (,) and an internal data bus coupling together a first parallel port (,A), a second parallel port (,B), a third parallel port (,C), an external memory interface (,), and a data input/output of the first cache and the second cache.