Semiconductor memory cell

Abstract

A semiconductor memory cell is configured using a sense amplifier and a memory cell containing MOS transistors. In a write cycle, the sense amplifier inputs write data to accumulate charges in the memory cell. In a read cycle, the sense amplifier outputs read data in response to the charges accumulated in the memory cell. A cell array is configured using sense amplifiers and memory cells, which are arranged in a matrix form in such a way that each sense amplifier is connected with the memory cells which are arranged in a same column. In addition, a pair of a write word line and a read word line are shared by the memory cells which are arranged in a same row, while a pair of a write bit line and a read bit line are shared by the memory cells which are arranged in a same column. Further, the sense amplifier is connected with the pair of the write bit line and read bit line. The write word line is arranged between the read word line and a ground line having a ground level. Thus, it is possible to stabilize the write word line in level because its adjoining write word line hardly interferes with the write word line at a random-access mode. In addition, by reducing the duration in writing of data into the memory cell, it is possible to prevent charges accumulated in the memory cell from easily leaking onto the write bit line.