The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 13, 2001
Filed:
Nov. 09, 2000
Jack J. Early, Perth Amboy, NJ (US);
AT&T Corporation, Middletown, NJ (US);
Abstract
An apparatus and a method for using at least two multiphase AC power sources to provide seamless uninterruptible power to a common load by isolating a faulty phase or source upon detection of a fault in one of the sources or in one of the phases thereof. To combine at least two three-phase power sources in parallel, for example, the apparatus includes a power paralleling circuit comprising two three-phase silicon controlled rectifier (SCR) bridges and a controller. Each bridge receives power from one of two separate and/or independent three-phase power sources. The controller monitors the status or condition of respective phases of power and selectively gates an associated SCR in each bridge so as to simultaneously power the common load from the two sources. Isolation switches are located in series with each phase circuit of each power supply. In the event of a fault, e.g., a loss of phase synchronization between corresponding phases of the respective power sources, an over-voltage condition of a phase, an under-voltage condition of a phase, etc., the controller issues gating signals to the appropriate SCR(s) or isolation switch(es) to isolate the defective phase(s) or power source from the load. In an alternative embodiment, an alarm is issued to alert maintenance personnel of a fault condition. A corresponding method for achieving the aforestated fault tolerance is also disclosed.