The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2001

Filed:

Nov. 13, 2000
Applicant:
Inventors:

Norio Koizumi, Suwa, JP;

Masahiko Tsuchiya, Suwa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 3/18 ; H02M 7/00 ; H02M 7/19 ;
U.S. Cl.
CPC ...
H02M 3/18 ; H02M 7/00 ; H02M 7/19 ;
Abstract

A semiconductor device that is capable of preventing erroneous operation such as momentary lighting, comprising a booster circuit to which first and second power supply potentials VDD and VSS are supplied from an external power source, for boosting the absolute value of the potential difference therebetween and charging the boosted potential to a capacitor. This booster circuit has a plurality of transistors and a plurality of capacitors, and the boosted potential is charged to one of the plurality of capacitors in accordance with how the plurality of transistors are turned on or off. The gates of a plurality of transistors are connected to output lines of first and second NAND circuits, to which the output of a comparator is input through a buffer. The output of the comparator is at a low level when the second power supply potential VSS is higher than a reference potential VREG, such as when the power is forcibly cut, in which case the charge in one of the plurality of capacitors is discharged, based on the outputs from the first and second NAND circuits.


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