The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 13, 2001
Filed:
Aug. 18, 2000
Method of fabricating various-sized passivated integrated circuit chips from a borderless gate array
Applicant:
Inventors:
Massimo Antonio Sivilotti, Sierra Madre, CA (US);
John Edward Tanner, Pasadena, CA (US);
Jin Luo, Monrovia, CA (US);
Assignee:
Tanner Research, Inc., Pasadena, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1301 ;
U.S. Cl.
CPC ...
H01L 2/1301 ;
Abstract
Effective passivation structures and guard rings can be formed in borderless gate arrays by forming the gates in an array of discrete blocks separated by thin scribe lines in which the substrate is not covered by gates. Diffusions for guard rings can be formed in the substrate for guard ring purposes, and passivation structures can be sealingly attached to the substrate. Various circuit metalizations such as discrete layers or different circuits can be produced with a single mask by covering all but a selected portion of the mask during exposure.