The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 13, 2001

Filed:

Jun. 30, 2000
Applicant:
Inventors:

Kee Jeung Lee, Seoul, KR;

Kwang Chul Joo, Kyoungki-do, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/18242 ;
U.S. Cl.
CPC ...
H01L 2/18242 ;
Abstract

Disclosed is a method of forming a capacitor for a semiconductor memory device according to the present invention. The method includes the steps of: forming a lower electrode on a semiconductor substrate; performing a surface-treatment process to prevent a natural oxide layer from generating on the surface of the lower electrode; forming a TaON layer on the upper part of the surface-treated lower electrode by a reaction of Ta chemical vapor, O,gas and NH,gas; crystallizing the TaON layer; and forming an upper electrode on the upper part of the TaON layer, wherein the TaON layer is formed in a low pressure chemical vapor deposition (LPCVD) chamber equipped with a shower head injecting Ta chemical vapor, O,gas and NH,gas on an upper part thereof and at a temperature of 300 to 600° C. with pressure of 0.1 to 10 Torr; wherein the TaON layer is formed in the LPCVD chamber that a first injector to which Ta chemical vapor and O,gas are injected and formed at one side-wall of the TaON layer and a second injector to which NH,gas is injected and formed at the other side-wall opposed to the first injector, thereby injecting reaction gases in a counter-flow state, and the TaON layer is formed at a temperature of 300 to 600° C. with pressure of 0.1 to 10 Torr; wherein the TaON layer is formed in the LPCVD chamber that a first injector to which Ta chemical vapor and O,gas are injected and formed at one side-wall of the TaON layer and a second injector to which NH,gas is injected and formed at the other side-wall opposed to the first injector, thereby injecting reaction gases in a counter-flow state, and the TaON layer is formed at a temperature of 300 to 600° C. with pressure of 0.1 to 10 Torr.


Find Patent Forward Citations

Lee, Kee. (2001). Method of forming a capacitor for a semiconductor memory device (U.S. Patent No. 6316307). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6316307

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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