The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2001
Filed:
Mar. 01, 1999
Donald Lee Freerksen, Rochester, MN (US);
Gary Michael Lippert, Kasson, MN (US);
John D. Irish, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A memory cache system is used in a multiprocessor environment. The first processor accesses data using a first level,cache, and the second processor accesses data using a second level,cache. A storage control circuit is positioned between the first and second level,caches and a level,cache and main memory. The level,cache maintains copies of data in main storage and further maintains an indication of those level,caches having copies of data and whether those copies have been modified. When a processor accesses data that is not resident in the connected level,cache, a request is delivered to the level,cache for this data. The level,cache then determines whether it can return a copy of the data to the level,cache or must access the data from main memory. Also, when the level,cache determines that another level,cache is storing a modified copy of the data, the level,cache returns to the storage control circuit a pointer to the level,cache having the modified copy of the data; the storage control circuit then causes the level,cache having a modified copy of the data, to transfer the modified data to the requesting level,cache without returning the data to the level,cache or main memory. This ameliorates the effects of repeated writes to the same data by the multiple processors.