Phase-locked loop

Abstract

The present invention is concerned with a PLL comprising the phase comparator,, loop filter,, VCO,and loop counter,, wherein there are further provided a prediction window circuit,for outputting HWIN (prediction window signal) for predicting the point at which the REF (reference signal) is generated, an omission compensation circuit,for detecting the omission of the REF at the time when HWIN is outputted and outputting d.VARX (the second correction signal) to offset the phase difference between d.REFX (the first correction signal) and the VAR (comparison signal) so that the phase comparator,outputs the signals Ph,and Ph,corresponding to the phase difference between the VAR and the d.REFX and the signals Ph,and Ph,corresponding to the phase difference between d.REFC and d.VARX when the omission of the REF has occurred, thereby enabling proper compensation for omission to be made and stable CLK (clock) to be generated even when VCO,having a very wide frequency variation range is used. Further, a circuit for generating the gate control signal Gc by advancing the phase of the VAR by 1 clock so that not only the 3-state signal corresponding to the phase difference between the REF and VAR can be outputted but also the 3-state buffers, which can be controlled in active state according to the signal Gc can be made available, whereby accurate control voltage corresponding to the phase difference can be outputted to the VCO to generate stable CLK even when the phase difference between the REF and VAR is close to 0.