The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2001
Filed:
Mar. 16, 2000
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A semiconductor integrated circuit has an internal clock signal generator circuit and a data input/output circuit. The internal clock signal generator circuit includes a clock receiver, a synchronous delay control circuit, a clock driver, an output control circuit, a delay monitor, and a control signal generator circuit. Accordingly, in a delay measuring mode, a delay in the input signal is set in the delay monitor based on a measurement start signal and a measurement stop signal. After completion of the delay measuring mode, the delay monitor causes the signal CLK, outputted from the clock receiver, to lag behind by a delay set in the delay measuring mode. Further, the delay monitor outputs the delayed signal to the synchronous delay control circuit.