The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 06, 2001
Filed:
Dec. 15, 1999
Janardhanan S. Ajit, Sunnyvale, CA (US);
Hung Pham Le, San Jose, CA (US);
Exar Corporation, Fremont, CA (US);
Abstract
The present invention provides a buffer circuit that can tolerate over-voltage, and a method for protecting buffer circuits from over-voltage. Specifically, the buffer circuit can operate at lower voltages (e.g., 3.3 V) and interface with other circuits that operate at higher voltages (e.g., 5 V). In a preferred embodiment, the buffer circuit has a pre-driver circuit having a pull-up circuit coupled to an interface node via a PMOS switch transistor. The pre-driver biasing circuit is configured to decouple the pull-up circuit from the input voltage source when an input voltage at the interface node exceeds the VDD voltage by a threshold voltage. The buffer circuit has a first biasing transistor that ties an N-well of the integrated circuit to the VDD voltage source when a control node of a PMOS driver transistor is in a first logic state, and a second biasing transistor that ties the N-well to the VDD voltage source when the control node of the PMOS driver transistor is in a second logic state.