Pmos device having a layered silicon gate for improved silicide integrity and enhanced boron penetration resistance

Abstract

The present invention provides a process for forming a sub-micron p-type metal oxide semiconductor (PMOS) structure on a semiconductor substrate. The process includes forming a gate oxide on the semiconductor substrate, forming a gate layer on the gate oxide by depositing a first gate layer on the gate oxide at a first deposition rate and depositing a second gate layer on the first layer at a second deposition rate to provide an improved stress accommodation within the gate structure. The process further includes forming a silicide dopant barrier on the gate. Due to the presence of the improved stress accommodation in the gate, the integrity of the silicide dopant barrier is substantially enhanced. This increased silicide integrity prevents significant damage to the silicide dopant barrier layer during subsequent fabrication processes. As such, the dopant barrier is able to provide the intended degree of resistance to dopant penetration, for example boron, during the formation of source and drain regions adjacent the gate structure.