The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2001

Filed:

Jul. 05, 2000
Applicant:
Inventors:

Takeshi Kishida, Hyogo, JP;

Akinori Kinugasa, Tokyo, JP;

Yoji Nakata, Tokyo, JP;

Tomoharu Mametani, Tokyo, JP;

Shigenori Kido, Tokyo, JP;

Yukihiro Nagai, Tokyo, JP;

Hiroaki Nishimura, Tokyo, JP;

Jiro Matsufusa, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/120 ;
U.S. Cl.
CPC ...
H01L 2/120 ;
Abstract

Provided is a method of manufacturing a semiconductor device having a capacitor above a semiconductor substrate, with which it is possible to reduce the number of steps and the cost of manufacture. Specifically, a polysilicon layer (,) in which impurity is diffused is deposited on the entire surface including the inside of a hole (,A). An etching process of the polysilicon layer (,) is performed to form a storage node electrode composed of the polysilicon layer (,) remaining on the bottom and side of a groove for metallization (,) and in the hole (,A). The storage node electrode is broadly divided into a storage node electrode body disposed on the bottom and side of the groove for metallization (,), and a plug part disposed in the hole (,A). The storage node electrode is electrically connected via the plug part to a diffused region (,) of a semiconductor substrate (,).


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