The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 2001
Filed:
May. 01, 2000
Heiji Ikoma, Nara, JP;
Yoshitsugu Inagaki, Osaka, JP;
Hiroyuki Konishi, Osaka, JP;
Koji Oka, Osaka, JP;
Akira Matsuzawa, Kyoto, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
In order to reduce power consumption, a power supply for a digital circuit portion is shut off, so that the output voltage of the power supply becomes the zero level. A CMOS (complementary metal oxide semiconductor) inverter has a P-channel FET (field effect transistor) with a gate electrode formed of P-type polysilicon. A source electrode of the P-channel FET is connected to the power supply and a back gate electrode of the P-channel FET is in direct connection with the aforesaid source electrode. The P-channel FET is placed in a state of not functioning as a transistor when the power supply is shut off in a low power consumption mode. However, in order to prevent the P-channel FET from undergoing characteristic degradation in that mode, there is the provision of a pull-down switch capable of fixing, in the mode, the voltage of the gate electrode of the P-channel FET at the zero level.