The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 30, 2001
Filed:
Nov. 09, 2000
Bernd Goebel, München, DE;
Emmerich Bertagnolli, München, DE;
Josef Willer, Riemerling, DE;
Barbara Hasler, Stockdorf, DE;
Paul-Werner von Basse, Wolfratshausen, DE;
Siemens Aktiengesellschaft, Munich, DE;
Abstract
The SRAM cell arrangement comprises six MOS transistors per memory cell that are fashioned as vertical transistors. The MOS transistors are arranged at sidewalls of trenches (G,G,G,). Parts of the memory cell such as, for example, gate electrodes (Ga,Ga,) or conductive structures (L,) fashioned as spacer are contacted via adjacent, horizontal, conductive structures (H,) arranged above a surface (O) of a substrate (S). Connections between parts of memory cells ensue via third conductive structures (L,) arranged at the sidewalls of the depressions and word lines (W) via diffusion regions (D,) that are adjacent to the sidewalls of the depressions within the substrate (S), via first bit lines, via second bit lines (B,) or/and via conductive structures (L,L,, L,) that are partially arranged at different height with respect to an axis perpendicular to the surface (O). Contacts (K,) contact a plurality of parts of the MOS transistors simultaneously.