The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 30, 2001

Filed:

Mar. 17, 1997
Applicant:
Inventors:

Taiji Ema, Kawasaki, JP;

Kazuo Itabashi, Kawasaki, JP;

Shinichiroh Ikemasu, Kawasaki, JP;

Junichi Mitani, Kawasaki, JP;

Itsuo Yanagita, Kawasaki, JP;

Seiichi Suzuki, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/18238 ;
U.S. Cl.
CPC ...
H01L 2/18238 ;
Abstract

The semiconductor device comprises a semiconductor substrate,of a first conduction-type, first wells,of a second conduction-type formed in a first region on the primary surface of the semiconductor substrate,, a second well,formed in a second region on the primary surface of the semiconductor substrate,other than the first region, a third well,of the first conduction-type formed in the first well, and high-concentration impurity-doped layers,of the first conduction-type formed in deep portions of the semiconductor substrate spaced from the primary surface of the semiconductor device in device regions. In the semiconductor device having triple wells according to the present invention, the high-concentration impurity-doped layers are formed in deep portions inside of the device regions. Accordingly, in the case where the wells have a low concentration so that the transistors have a low threshold voltage, the deep portions of the wells can independently have a high concentration. As a result, punch-through between the source/drain diffused layer of the transistor formed in the well in the well (double wells), and the well outside of the double wells can be prevented. This structure is also effective to prevent latch-up.


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