The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 2001

Filed:

Jul. 21, 1999
Applicant:
Inventors:

John G McBride, Ft Collins, CO (US);

Jan Kok, Fort Collins, CO (US);

Assignee:

Hewlett-Packard Company, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract

The present invention is directed to a system and method for identifying multiplexers from a netlist. In accordance with one aspect of the invention, a method identifies multiplexers from a netlist by identifying both an input node and an output node of a pass gate. The method then identifies all FETs that are channel connected to the output node, and evaluates all FETs that are identified as being channel connected to the output node, to determine whether they are pass FETs. Finally, the method determines whether at least one of the identified pass FETs has an output that is the same node as the output node and an input that is not the same node as the input node. In accordance with another aspect of the invention, the method identifies a node in the netlist that is an output node of a first pass FET and identifies at least one other pass FET that has an output that is the same node as the output node. Finally, the method evaluates the at least one other pass FET to determine whether an input of that other at least one other pass FET is not the same node as an input node of the first pass FET.


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