The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 23, 2001
Filed:
Jul. 24, 2000
Applicant:
Inventor:
Steven Robert Masteller, St. Paul, MN (US);
Assignee:
Theseus Logic, Inc., St. Paul, MN (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/314 ;
U.S. Cl.
CPC ...
G06F 1/314 ;
Abstract
An asynchronous FIFO using Asynchronous NULL Convention LOGIC (NCL) to facilitate interfacing between multiple non-synchronous systems with a minimum of design and verification. Multiple interfaces, configurations, means for minimizing latency, and capabilities for datastream processing are also incorporated.
Masteller, Steven. (2001). System for facilitating interfacing between multiple non-synchronous systems utilizing an asynchronous fifo that uses asynchronous logic (U.S. Patent No. 6308229). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6308229
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile