Asynchronous transfer mode controller and atm control method thereof and atm communication control apparatus

Abstract

An asynchronous transfer mode (ATM) controller includes a buffer memory, a transfer circuit which transfers packet data between the buffer memory and an internal memory of an associative terminal unit with a data block of predetermined length being a unit therefor, a cell transmit circuit section that subdivides or “slices” the predetermined length data block sent from the terminal memory to the buffer memory into data cells which are then sent forth to the ATM network, a cell receive control circuit operable to reconstruct or re-assemble those data cells received from the ATM network over a transfer path thereby forming in the buffer memory a predetermined length data block, and a transfer control circuit operable to permit or “instruct” the transfer circuit to transfer the predetermined length data block between the buffer memory and the terminal memory and also instruct both the cell transmit control circuit and the cell receive control circuit to transfer the data cells between the buffer memory and the ATM network over the transfer path, thereby enabling accommodation of a variety of kinds of setup configurations and/or any possible changes or alterations in ATM protocol processing as assigned to a microprocessor.