Semiconductor memory device and signal line shifting method

Abstract

A semiconductor memory device comprises: a memory cell array having memory cells arranged in the form of a matrix; a redundant column cell array configured to relieve a defective column of the memory cell array; a decoder circuit configured to decode an address to select a memory cell in the memory cell array; a plurality of data lines, to which data read out from the memory cell array or data to be written in the memory cell array, corresponding to a plurality of columns, is transferred by the decoder circuit; a data line, to which data read out from the redundant column cell array or data to be written in the redundant column cell array is transferred; a data line shift circuit configured to shift, one by one, data line and the spare data line, which are arranged on one side of a data line serving as a starting point, to which data of a defective column is to be transferred when the defective column is accessed, to connect the data line and the spare data lines to data input/output lines; a selecting circuit configured to store a correspondence between the address of the defective column and a shift point, which is assigned to each of the data input/output lines so as to increase by 1 of every starting point of the data line shift by the data line shift circuit, and configured to output a selecting signal corresponding to the shift point when the address of the defective column is inputted; and a shift control circuit configured to output a shift control signal to the data line shift circuit by comparing the selecting signal, which is outputted from the selecting circuit, with the shift point.