The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 23, 2001
Filed:
Feb. 23, 2000
Lawrence William Friedrich, Escondido, CA (US);
Jerry Ihor Tustaniwskyj, Mission Viejo, CA (US);
James Mason Brafford, Mission Viejo, CA (US);
James Wittman Babcock, Escondido, CA (US);
Unisys Corporation, Blue Bell, PA (US);
Abstract
An electromechanical apparatus for testing integrated chips includes a chip holding subassembly, a power converter subassembly, and a temperature regulating subassembly, which are squeezed together in multiple sets, by respective pressing mechanisms. One benefit which is achieved with this electromechanical apparatus is that by pressing the temperature regulating subassembly against the chip holding subassembly, heat can be added/removed from the chips by conduction; and thus the temperature of the chips can be regulated accurately. Another benefit which is achieved with this electromechanical apparatus is that by pressing the power converter subassembly against the chip holding subassembly, the distance between the chips that are tested and the power supplies for those chips is made small. Consequently, the chip voltages can easily be kept constant while the chip power dissipation changes rapidly as the chips are tested. Another benefit of this electromechanical apparatus is that physical contact between the three subassemblies is made quickly, and is broken quickly, by the pressing mechanisms. This quick quick-connect/quick-disconnect feature is very useful in a chip testing environment.