The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 23, 2001
Filed:
Mar. 15, 2000
Koji Shirai, Kawasaki, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A MOSFET formed on an SOI substrate secures a high withstand voltage and a reduced element area. The SOI substrate includes an insulator layer and an n,-type semiconductor layer formed on the insulator layer. The MOSFET consists of a p-type impurity diffusion region formed on the semiconductor layer, an n,-type source region formed in a surface area in the p-type impurity diffusion region, a gate insulating layer formed on the p-type impurity diffusion region and covering a region between the source region and the semiconductor layer, a gate electrode formed on the gate insulating layer, an n,-type drain region formed on the semiconductor layer at a predetermined position separated from the p-type impurity diffusion region, and an n-type well formed around the drain region. The impurity concentration of the n-type well is lower than that of the drain region and higher than that of the semiconductor layer.