Information packet reception indicator for reducing the utilization of a host system processor unit

Abstract

A reception indicator circuit is provided for use in an apparatus, wherein the apparatus enables a host system to receive information packets from a medium. The reception indicator circuit has a delay calculator, a byte count comparator and a signal asserter. The delay calculator selects and reads a reference delay value in one of N number of length-delay data storage elements. A reference length value contained in the one of N number of length-delay data storage elements corresponds to a length value of an information packet being received by the apparatus. The length value of the information packet is determined based on data in the information packet. The byte count comparator detects when the reference delay value number of bytes in the information packet have been received by the apparatus. The signal asserter asserts a reception indication signal when the byte count comparator detects that the reference delay value number of bytes in the information packet have been received by the apparatus. Alternatively, the reception indicator circuit may include a delay calculator that either calculates or selects an interrupt time. In such an alternate reception indicator circuit, the byte count comparator may be replaced by a delay comparator that determines when the interrupt time has elapsed. After the interrupt time has elapsed, the signal asserter asserts the reception indication signal. The apparatus may be a network peripheral, and the medium may be a communications network.