Automated test vector generation and verification

Abstract

Disclosed is a method for generating AVF test file data for use in testing a simulation of an integrated circuit design, and verifying the generated AVF test file data before they are delivered to a physical silicon version of the integrated circuit design. The generation method includes providing a map file that contains a plurality of identifying statements for each multiple port I/O cell (or also including single port I/O cells) in the integrated circuit design. Then, generate a verilog executable file for the integrated circuit design. The verilog executable file is configured to contain data associated with the map file, a netlist of the integrated circuit design, output enable data derived from the netlist, and AVF data conversion information. The method further comprises executing the verilog executable file along with a test bench that includes the netlist of the integrated circuit design, a set of test files, and models. The execution is configured to produce the AVF test file data and a DUT timing file data. The generated data is then processed through a verification loop that is configured to identify in a log all of the possible errors with the generated test data. The input data used to generate the AVF test file data may then be modified to enable the re-generation of new AVF test file data and new DUT timing file data. If errors are still present, the loop may again be re-run, if the errors are of the kind that would necessitate correction. Once the verification loop has been run to the satisfaction of the test engineer, the test vector data can be applied to the physical test station for use on the physical silicon chip.