Worst case design parameter extraction for logic technologies

Abstract

The present invention provides for more realistic worst case extreme determinations for an integrated circuit as compared to conventional techniques. In particular, the present invention provides a framework which affords for improved linkage between semiconductor manufacturing process parameters and an integrated circuit designed based on the electrical properties of cells making up the integrated circuit. The present invention divides an integrated circuit into simple standard cells and more complex cells. For simple standard cells (e.g., XOR, NAND, NOR, inverter), a pre-modeling step is performed to model the simple standard cell as a circuit in order to obtain gate delay and power consumption distributions related thereto. Such pre-modeling affords for more accurate semiconductor physical parameters to be employed to generate the normalized distribution of the integrated circuit which in turn provides for better worst case extremes. More complex cells are modeled with I/V curves distributions for understanding the effects of semiconductor device attribute choices, such as channel length, effects of “guard band” or manufacturability of such devices. As a result of the present invention, IC circuits may be manufactured with more realistic or practical worst case extreme parameters and thus, more densely designed and manufactured without substantially sacrificing operability.