The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2001

Filed:

Jun. 23, 2000
Applicant:
Inventors:

Joerg Vollrath, Richmond, VA (US);

Michael Fera, Glen Allen, VA (US);

Philip Moore, Richmond, VA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 ;
U.S. Cl.
CPC ...
G11C 5/06 ;
Abstract

A memory array, in accordance with the invention, includes a plurality of memory cells disposed in an array. A plurality of bitlines are included for reading and writing data to and from the memory cells. The plurality of bitlines include a first group of bitlines and a second group of bitlines. Each bitline of the first group is interposed between bitlines of the second group, and each bitline of the second group is interposed between bitlines of the first group. The first group of bitlines are active when the second group of bitlines are inactive, and the second group of bitlines are active when the first group of bitlines are inactive such that adjacent inactive bitlines provide a shield to prevent cross-coupling between active bitlines.


Find Patent Forward Citations

Vollrath, Joerg. (2001). Shielded bit line architecture for memory arrays (U.S. Patent No. 6304479). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6304479

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…