The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2001

Filed:

May. 20, 1999
Applicant:
Inventors:

Richard Mett, Santa Clara, CA (US);

Siamak Salimian, Sunnyvale, CA (US);

Assignee:

Applied Materials Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02N 1/300 ;
U.S. Cl.
CPC ...
H02N 1/300 ;
Abstract

A method and apparatus for retaining a substrate, such as a semiconductor wafer, upon an electrostatic chuck within a semiconductor wafer processing system. Specifically, the apparatus contains high voltage, DC power supply that is capable of both sourcing and sinking current at any polarity of output voltage level. This power supply is coupled to at least one electrode of an electrostatic chuck. Consequently, the power supply can be used to dynamically control the chucking voltage to apply a negative potential difference between said wafer and chuck.


Find Patent Forward Citations

Mett, Richard. (2001). Method and apparatus for minimizing plasma destabilization within a semiconductor wafer processing system (U.S. Patent No. 6304424). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6304424

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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