The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2001

Filed:

Jul. 15, 1999
Applicant:
Inventor:

Ravindra Shenoy, Sunnyvale, CA (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B 5/24 ; H03K 3/00 ;
U.S. Cl.
CPC ...
H03B 5/24 ; H03K 3/00 ;
Abstract

A delay cell, a method for generating a delay, and a differential ring oscillator are disclosed. The delay cell provides a stable delay with a low voltage power supply, and has a high power supply rejection ratio. The delay cell generally comprises a first and second input receiver on a first and second branch, respectively, to receive an input to control a current on each branch, each branch includes an output node capacitively coupled to a power supply. Each branch may include a current source coupled between the output node and the power supply and/or a lower limit clamp coupled between the output node and the power supply to maintain an output at the output node above a lower limit. The delay cell may also include a first and a second current diverter coupled to the first and second branch for diverting current on the first and second branch away from the first and second input receiver, respectively. An upper limit clamp may be coupled between the power supply and the first and second current diverters to maintain the output below an upper limit. Inputs to the lower and upper limit clamps may be generated relative to the power supply. The delay cell may further include a tail current source coupled between ground and the input receivers and an upper clamp current source coupled between ground and the first and second current diverters.


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