The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2001
Filed:
Dec. 23, 1999
Applicant:
Inventors:
Assignee:
Nortel Networks Limited, St-Laurent, CA;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 1/756 ;
U.S. Cl.
CPC ...
H03K 1/756 ;
Abstract
The present invention relates to a bias circuit for biasing a depletion mode power transistor. The bias circuit includes a voltage offset circuit and a transistor, where the voltage offset circuit is serially coupled between the gate terminal of the depletion mode power transistor and the drain terminal of the transistor. The bias circuit generates a bias voltage that, when applied to the gate terminal of the depletion mode power transistor, maintains a substantially constant drain current through the power transistor over a range of threshold voltages caused by process and temperature variations.