The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2001

Filed:

Mar. 22, 2000
Applicant:
Inventor:

Tsuyoshi Hirakawa, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/00 ;
U.S. Cl.
CPC ...
H03L 7/00 ;
Abstract

The present invention provides a mode setting determination signal generation circuit for generating a mode setting determination signal based on a power-on signal applied during power-up, including signal generation means for generating an output signal fixed either to a high or low level, a first logic circuit section for outputting a signal based on a NOR or OR logic between the output signal from the signal generation means and the power-on signal, a second logic circuit section for outputting a signal based on a NAND or AND logic between a power-on signal having a polarity opposite to that of the power-on signal and the output signal from the signal generation means, a third logic circuit section for outputting a signal based on a NAND or AND logic between a signal at a mode setting determination signal output terminal thereof and the output signal from the second logic circuit section, a transfer gate circuit section for outputting either the output signal from the third logic circuit section or a mode setting signal as an output signal based on a mode setting control signal, and a fourth logic circuit section for outputting a signal based on a NAND or AND logic between the output signal from the transfer gate circuit section and the output signal from the first logic circuit section.


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