The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2001
Filed:
Sep. 15, 2000
Applicant:
Inventor:
Thomas A. Kean, Edinburgh, GB;
Assignee:
Xilinx, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 1/9177 ;
U.S. Cl.
CPC ...
H03K 1/9177 ;
Abstract
A field programmable gate array configured to use RAM control signals as routing and/or logic resources. By using RAM bit lines as routing, and/or to implement Wire-OR functions, and/or with word lines to implement PAL functions, one may increase the efficiency of lines normally used only for programming the control memory.
Quick Actions:
Kean, Thomas. (2001). Fpga using ram control signal lines as routing or logic resources after configuration (U.S. Patent No. 6304103). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6304103
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