The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2001
Filed:
Sep. 13, 2000
Seungyoon P. Song, Palo Alto, CA (US);
Elan Research, Palo Alto, CA (US);
Abstract
A repairable dynamic programmable logic array (DPLA) is disclosed. The repairable DPLA comprises of AND and OR logic planes and redundant term generators in the logic planes. A redundant term generator comprises a plurality of reprogrammable evaluate modules so that each input to the logic plane can be programmed to affect the redundant term generator. For repairing a defective AND term generator, a redundant output select module connected to the output of the redundant AND term generator is added to each of the OR term generators, including the redundant OR term generators. To repair a defective AND term generator, the wired-NOR function programmed into the defective AND term generator is programmed into the redundant AND term generator. The redundant output select module is programmed to be affected by the redundant AND term output if the associated OR term generator is programmed to be affected by the defective AND term generator. The defective AND term generator is disabled by not enabling its discharge transistor. The redundant AND term generator is enabled by enabling its discharge transistor during evaluate phases. For repairing a defective OR term generator, an output replacement module is added between the OR term generator outputs and the PLA outputs. To repair a defective OR term generator, the wired-NOR function programmed into the defective OR term generator is programmed into the redundant OR term generator. The output replacement module is configured to steer the redundant OR term output to the PLA output that is connected to the defective OR term output. The defective OR term generator is disabled by not enabling its discharge transistor. The redundant OR term generator is enabled by enabling its discharge transistor during evaluate phases.