The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2001

Filed:

Jun. 02, 2000
Applicant:
Inventor:

Yoshio Nishihara, Nakai-machi, JP;

Assignee:

Fuji Xerox Co., LTD, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/500 ; G06F 7/38 ;
U.S. Cl.
CPC ...
H01L 2/500 ; G06F 7/38 ;
Abstract

The invention is made to implement technique similar to multicontext technique without using a configuration memory for storing plural circuit information pieces that causes deterioration of circuit performance, increase of power consumption, increase of processes and increase of the manufacturing cost. Therefore, in a programmable logic device, a circuit information storage different from the configuration memory and a circuit information editor for generating circuit information of a specified circuit using circuit information stored in the circuit information storage are provided. In the circuit information storage, circuit information of plural circuits is stored in a compressed state. When specification information of the circuit information of a reconfigured circuit is input to a programmable logic circuit, the circuit information editor reads required circuit information from the circuit information storage, decompresses compressed circuit information, generates circuit information specified in the specification information, transfers the generated circuit information to a configuration memory and reconfigures the circuit.


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