Phase detector that samples a read signal at sampling points and delay

Abstract

A phase detector determines a phase error value dependent on the relative phase between a local oscillator signal, used for the system clock, and an input signal received over a PR (a, b, b, a) channel. The error value is used to lock the phase and frequency of an input signal to the phase and frequency of the clock in a phase-lock loop (FIG.,, not shown). The input signal is sampled at regular intervals in accordance with the local oscillator signal, and the sampled values provided on a line,. A threshold slicer,selects an ideal sample value for a sampling point by comparing the sampled values with thresholds received on threshold inputs,to,. A subtracter,determines a difference value which corresponds to a difference between the ideal sample value and the actual sample value for that sampling point. A subtracter,and a delay register,operate to determine the sense of change to the ideal sample value from a ideal sample value for a preceding sampling point. A second subtracter,and a second delay register,determine the sense of change to the ideal sample value for a preceding sampling point from a ideal sample value for a twice preceding sampling point. The phase error value provided is dependent on the senses of change detected and on the difference value.