Interconnect structure with a passivation layer and chip pad

Abstract

The semiconductor device includes a silicon substrate, a first metal pattern layer which is deposited on the silicon substrate, and an inter metal dielectric which is deposited on the silicon substrate including the first metal pattern layer and on which a connection hole is formed to partially expose the upper surface of the first metal pattern layer, the connection hole having concave corner portion formed on a side thereof. A second metal pattern layer is deposited on the inter metal dielectric and electriacally interconnects to the first metal pattern layer by the connection hole. A passivation layer coats the silicon substrate including the second metal pattern layer and the concave corner portion and has an opening to partially expose the second metal pattern layer for electrically connecting the semiconductor device to external circuitry. The passivation layer extends beyond the concave corner portion such that when the passivation layer is etched, the concave corner portion remains coated with the passivation layer to thereby protect the concave corner portion from damage due to subsequent processes. The first metal pattern layer comprises a Ti/TiN layer, an Al layer, and a TiN layer, and the second metal pattern layer comprises a Ti layer and an Al layer.