The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 09, 2001
Filed:
Nov. 02, 1998
Luc M. Burgun, Creteil, FR;
Frederic M. Emirian, Paris, FR;
Other;
Abstract
An apparatus is programmed to automatically remove timing hazards from a circuit design. The apparatus identifies certain level sensitive storage circuit elements in the circuit design. The identified level sensitive storage circuit elements are those having timing hazards. The timing hazards arise as a result of potential skews between the reference signal for the circuit design and the synchronization signal controlling each storage circuit element. A skew, introduced by a gated or divided clock, cannot be assured to be within a design tolerance limit. Therefore, the program enables the apparatus to transform the identified level sensitive storage circuit elements into level sensitive storage circuit elements controlled by synchronization signals that do not have potential skews with respect to the reference signal of the circuit design. The transformation, however, is accomplished without altering the functionality of the circuit design. In effect, the apparatus automatically removes some or all of the timing hazards by determining the appropriate transformation for each of the identified level sensitive storage circuit elements.