Signal gating controller for enhancing convergency of mlt3 data receivers

Abstract

A signal gating controller for recovering true data signal pulses while gating out false data signal pulses which are generated and prevent convergence when recovering a multilevel data signal, such as an MLT3 Ethernet signal, which has been severely over-equalized. A signal slicing circuit generates two data peak signals: one data peak signal identifies occurrences of positive data signal peaks and is asserted when the input data signal level has transitioned beyond a value which is intermediate to preceding zero and positive peak signal levels; the other data peak signal identifies occurrences of negative data signal peaks and is asserted when the input data signal level has transitioned beyond a value which is intermediate to preceding zero and negative peak signal levels. A signal gating control circuit sequentially latches such data peak signals to produce two gating control signals. Logical combinations of such gating control and data peak signals produce gated signals in which the true data peak signal pulses remain while the false data peak signal pulses due to severe over-equalization of the incoming data signal are removed.